i) Field of Invention
Embodiments of the present invention generally relate to transistors, and in particular to distributed heating (DH) transistor devices providing reduced self-heating.
ii) Description of Related Art
Electronic devices and integrated circuits have performance limits that are frequently set by the maximum allowable current density, voltage/electric field, and channel (or junction) temperature. Self-heating of these devices is undesirable as it reduces performance and lifetime. The channel temperature Tc is correlated with the device lifetime through the Arrhenius equation, and may be determined through simulations, theoretical models, or experimentally. Channel temperature directly affects the bandgap, electron mobility, electron saturation speed, pinch-off voltage, breakdown voltage, transconductance, saturation current, output power, and noise performance.
Reducing Tc typically leads to enhanced device performance, and reliable, sustainable operation. Heating in transistors may lead to memory effects which cause linearity degradation. Channel temperature is directly proportional to power dissipation through the thermal resistance constants. It also depends critically on the device layout. In the case of field effect transistors (FETs) and high electron mobility transistors (HEMTs), Tc increases with the thermal resistance constant, and depends on the gate-width, gate-length, gate-pitch, and substrate thickness and thermal conductivity. Transistor heating is a primary cause of memory effects which degrade linearity of power amplifiers, especially for modulated signals, for instance.
Conventional approaches, such as increasing gate-pitch dimension, result in larger device size and performance degradation especially at millimeter-wave frequencies. Additionally, transistor heating is a cause of memory effects which degrade linearity of power amplifiers, especially for modulated signals.